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This paper proposes an FFT-based method that separates random jitter from deterministic jitter in clock and data patterns, with a 10X reduction in test time. The method has been verified experimentally on a 2.5 Gbps clock pattern & 7-stage PRBS, and gives results that are comparable to existing methods.
Test Conference, 2007. ITC 2007. IEEE International
Date of Conference: 21-26 Oct. 2007