Referenced Items are not available for this document.
This paper proposes an FFT-based method that separates random jitter from deterministic jitter in clock and data patterns, with a 10X reduction in test time. The method has been verified experimentally on a 2.5 Gbps clock pattern & 7-stage PRBS, and gives results that are comparable to existing methods.
Published in:
Test Conference, 2007. ITC 2007. IEEE International
Date of Conference: 21-26 Oct. 2007
- Page(s):
- 1 - 8
- ISSN :
- 1089-3539
- E-ISBN :
- 978-1-4244-1128-3
- Print ISBN:
- 978-1-4244-1127-6
- INSPEC Accession Number:
- 10062108
- Conference Location :
- Santa Clara, CA
- Digital Object Identifier :
- 10.1109/TEST.2007.4437607
- Product Type:
- Conference Publications
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