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One of the major reliability concerns in nano-scale VLSI design is the time dependent negative bias temperature instability (NBTI) degradation. Due to the higher operating temperature and increasing vertical oxide field, threshold voltage (Vt) of PMOS transistors can increase with time under NBTI. In this paper, we examine the impact of NBTI degradation in memory elements of digital circuits, focusing on the conventional 6T SRAM array topology. Using an empirical NBTI model based on the reaction diffusion (RD) framework, we first examine the impact of NBTI degradation in critical performance parameters of SRAM array. These parameters include (1) static noise margin (SNM), (2) statistical read & write stability, and (3) standby leakage current (IDDQ). We show that due to NBTI, read stability of SRAM cell degrades, while write stability and standby leakage improve with time. Furthermore, using specific time trend of IDDQ degradation, we proposed efficient characterization technique to predict the lifetime behavior of SRAM array under NBTI.