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Silicon evaluation of longest path avoidance testing for small delay defects

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4 Author(s)
Turakhia, R. ; Integrated Circuit Design & Test Lab., Portland, OR ; Daasch, W.R. ; Ward, M. ; Van Slyke, J.

This work presents a silicon evaluation of testing for small-delay defects using an approach called longest path avoidance testing. The motivation for LPA testing is to improve outgoing product quality by identifying delay defects that escape critical path delay testing. Results from experiments run on high volume production 180 nm ASIC are quantified in terms of test escapes and reliability escapes. Techniques for modeling the impact of small-delay testing are discussed.

Published in:

Test Conference, 2007. ITC 2007. IEEE International

Date of Conference:

21-26 Oct. 2007