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A VLSI readout front-end architecture, dedicated for X-ray imaging, using specific capacitive silicon detectors, with capacitance ranging from 2 to 10 pF, is described. Critical design issues such as the noise optimization and the shaper implementation technique are addressed and the first performance - test results of a fabricated prototype in a 0.35-mum 3.3-V CMOS process, are presented. Important feature of the design is the novel CR - RC2 pulse-shaper configuration since in this section, transconductor circuits are used in order to provide a broad range of continuous variable peaking time, programmable gain and adjustable undershoot while still maintaining the noise performance and the required linearity of the specific radiation detection application. Regarding the readout ASIC performance characteristics, the power consumption is 1 mW per channel, the equivalent noise charge at 1.81-mus peaking time is 382 e- plus 21 e- per picofrard of detector capacitance. The topology achieves a conversion gain equal to 3.31 mV/fC and a linearity of 0.69%.
Circuits and Systems I: Regular Papers, IEEE Transactions on (Volume:55 , Issue: 7 )
Date of Publication: Aug. 2008