By Topic

Solar intensity X-ray spectrometer (SIXS) ASIC for a large dynamic range onboard BepiColombo ESA mission to Mercury

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

10 Author(s)
Farah F. Khalid ; STFC Rutherford Appleton Laboratory, Oxon, OX11 0QX United Kingdom ; Mark L. Prydderch ; Quentin Morrissey ; Paul Seller
more authors

The SIXS instrument is designed for detecting and measuring solar X-rays and solar energetic particles in a Mercury orbit onboard BepiColombo. The particle detector consists of a CsI(Tl) core detector and 5 GaAs surface detectors. The front-end electronics of the particle detector is implemented as an ASIC which requires a large dynamic range of 2,000e- to 1,500,000e- and an integral non-linearity (INL) < 3% for a temperature range of -30deg C to +55deg C. The SIXS ASIC test structure has been manufactured to determine performance of differential vs. single-ended designs for noise, power supply rejection and current consumption. The ASIC has 8 channels, each of which consists of a preamplifier, a CR-RC shaper, a peak hold, a comparator and a buffer, all designed using enclosed geometry transistors. There are 6 channels for GaAs detectors with 3 different preamplifier types consisting of a single-ended with pole zero compensation; single-ended without pole zero compensation and a differential configuration. There are 2 channels for Csl detectors with single- ended and differential preamplifier designs. This ASIC has been manufactured in a 0.35 mum CMOS process. The ASIC architecture and design flow are described including simulated and measured results.

Published in:

2007 IEEE Nuclear Science Symposium Conference Record  (Volume:2 )

Date of Conference:

Oct. 26 2007-Nov. 3 2007