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New time to digital converter, signal processing, data acquisition, calibration and test hardware for RatCAP

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11 Author(s)
Sachin S Junnarkar ; Brookhaven National Laboratory, Upton, New York 11973-5000, USA ; Jack Fried ; Sudeepti Southekal ; Sri Harsha Maramraju
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Altera Stratix II family Field Programmable Gate Array (FPGA) based realization of the 12 channel Time to Digital Converter (TDC), address serial decoder and PCI based DAQ system for the next generation of Rat Conscious Animal PET (RatCAP) is presented in detail. TDC realization approach using an FPGA is further investigated and resulting circuits are characterized. Previous generation RatCAP TDC characteristics are shown for comparison. TDC circuits were realized as a two stage solution. First stage of coarse TDC component consisted of binary counter running at system clock speed of 100 MHz, giving 10 ns resolution. Second stage of fine TDC component was realized to achieve sub nano second resolution with 625 ps LSB. Routing delays between Logic Array Blocks (LAB) combined with propagation delay of logic cells called LCELL were used to generate different clock phases, to achieve sub clock speed resolution TDC. Altera LogicLock toolset and assignment based approach were used for replicable and tighter placements of the supporting logic to achieve the required timing performance. PCI based custom designed board with two banks of Static Random Access Memory (SRAM) constituted the DAQ and control electronics. Test results with full 12 blocks, RatCAP front end electronics are presented. TDC realization and characterization is discussed in details.

Published in:

2007 IEEE Nuclear Science Symposium Conference Record  (Volume:6 )

Date of Conference:

Oct. 26 2007-Nov. 3 2007