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A 35mW 12 bits 25 MS/s pipelined analog to digital converter

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9 Author(s)

The design of a full integrated electronics readout for the next ILC ECAL presents many challenges. Low power dissipation is required, and it will be necessary to integrate together the very front-end stages with the analog to digital converter. We present here a 12 bits 25 MHz analog to digital converter using the pipe line architecture. Its' first stage is a charge redistribution sample and hold, then follow ten 1.5 bit sub-ADC and finally a 2 bit flash. A CMOS 0.35 mu process is used, and the dynamic range covered is 2V. The analog part of the converter can be quickly switched (a couple of mus) to a standby mode that reduces the DC power dissipation by a ratio of 1/1000. The size of the converter's layout including the digital correction stage is only 1.7 mm * 0.6 mm, and the total dc power dissipation is 35 mW.

Published in:

Nuclear Science Symposium Conference Record, 2007. NSS '07. IEEE  (Volume:4 )

Date of Conference:

Oct. 26 2007-Nov. 3 2007

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