Skip to Main Content
A robust network-on-chip (NoC) architecture is presented for a 2D mesh topology that uses wormhole routing with finite first-in-first-out (FIFO) buffer-based links and a minimal adaptive routing algorithm. In designing this NoC architecture, basic network problems such as dead- lock/livelock freedom and high throughput are considered. Additionally, some issues related with actual VLSI implementation, such as design complexity and simplicity of routing algorithm, are evaluated. To verify its efficiency, a simulation-based performance evaluation and an analytical method are used. In simulation, we compare our works with other designs using standard traffic patterns used in the literature. Also a new analytical performance model is proposed. Unlike previous wormhole and adaptive routing models, the model introduced copes with variable node buffer size as well as message length under uniform random traffic pattern. The analytical model is validated by comparing with the simulation-based model using the same traffic pattern. Major contribution here is the design of two different performance models for the proposed router in NoC architecture. Specifically, a simple and accurate analytical model for NoC communication for standard applications includes the effect of variable node buffer size as well as the message length. This is the first attempt in proposing an accurate analytical model for adaptive routers.