Referenced Items are not available for this document.
Systolic VLSI architectures for implementing the full-search block-matching algorithm are described. A large range of data rates can be efficiently covered by the proposed architectures. The input bandwidth problem for the search-area data is solved by on-chip line buffers, allowing a low frame-buffer access rate. An architecture for block-scan data input is described in detail. A VLSI realization with a low transistor count can be achieved by linear arrays in conjunction with compact memory blocks based on three-transistor cells
Published in:
Circuits and Systems, IEEE Transactions on
(Volume:36
,
Issue:
10
)
Date of Publication: Oct 1989
- Page(s):
- 1309 - 1316
- ISSN :
- 0098-4094
- INSPEC Accession Number:
- 3572601
- Digital Object Identifier :
- 10.1109/31.44347
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 August 2002
- Issue Date :
- Oct 1989
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