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A DSP architectural design for low bit-rate motion video codec

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4 Author(s)
Murakami, T. ; Mitsubishi Electr. Corp., Kamakura, Japan ; Kamizawa, K. ; Kameyama, M. ; Nakagawa, S.-I.

A new digital signal processor (DSP) architecture is presented. This DSP consists of the usual components, such as instruction set, buses, data memories, execution unit, address generators, sequencer, and direct memory access controller, optimized for video signal processing. A 24-bit 50-ns DSP called the digital image signal processor (DISP) has been developed using 1-μm CMOS technology. The performance of the DSP is evaluated by a benchmark test based on an actual video coding sequence. A multi-DSP configuration for a video codec that allows flexible algorithms and variable picture formats is studied. A low-bit-rate motion video codec can be built very easily using the DSPs presented by the authors

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Circuits and Systems, IEEE Transactions on  (Volume:36 ,  Issue: 10 )