Low-Power Programmable Pseudorandom Word Generator and Clock Multiplier Unit for High-Speed SerDes Applications

This paper presents the design of a low-power programmable pseudorandom word generator (PRWG) and a low-noise clock multiplier unit (CMU) for high-speed SerDes applications. The PRWG is capable of producing test patterns with sequence length of $2 ^{7} -1$, $2 ^{10} -1$, $2 ^{15} -1$, $2 ^{23} -1$, and $2 ^{31} -1~\hbox{b}$ according to CCITT recommendations, and the random word is 16-bit wide. High-speed and low-power operations of the PRWG are achieved by parallel feedback techniques. The measured jitter of the CMU is only 3.56 ${\hbox {ps}}_{\rm rms}$, and the data jitter at the PRWG output is mainly determined by the CMU. Implemented in an 0.18-$\mu{\hbox {m}}$ CMOS process, the power dissipation for the PRWG is only 10.8 mW, and the CMU consumes about 87 mW from a 1.8-V supply. This PRWG can be used as a low-cost substitute for external parallel test pattern generators.