By Topic

Wafer level chip stacked module by embedded IC packaging technology

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

11 Author(s)
Chien-Wei Chien ; EOL/ Ind. Technol. Res. Inst., Hsinchu ; Li-Cheng Shen ; Tao-Chih Chang ; Chin-Yao Chang
more authors

Wafer level chip stacked module by embedded IC packaging technology was studied in this paper. Wafers were treated to less than 50 mum thickness and then singulated. The prepared thin chips were stacked on to the base wafer and then embedded by dielectric layers (Ajinomoto build up film, ABF) lamination. Vias to both the pads on the analog chips and digital wafers were done by UV laser drilling process. After surface treatment and seed layer deposition, Cu plating process was adapted for the the via filling and traces patterning to form the interconnection between the chips and the component IO pads. Results of this study showed the benefits of the structure can provide more precise alignment and more reliable chip to wafer stacking without any voids or defects. Meanwhile, the presented wafer level process gives a much simple and cost effective package. By the described process integration, vertical chip stacked and embedded module within 300 mum thickness, excluding the solder ball, could be demonstrated. All the realization of this small size module will be revealed in detail. Severe reliability tests such as the 288degC solder dipping and 260degC level 3 pre-conditioning test were carried out to further clarify the component property. The corresponding failure analysis will be carried out to further clarify the key points of the whole demonstration.

Published in:

Microsystems, Packaging, Assembly and Circuits Technology, 2007. IMPACT 2007. International

Date of Conference:

1-3 Oct. 2007