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Wafer level chip stacked module by embedded IC packaging technology

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11 Author(s)
Chien-Wei Chien ; EOL/ Industrial Technology Research Institute, 195, Sec. 4, Chung Hsing Rd., Chutung, Hsinchu, Taiwan, China ; Li-Cheng Shen ; Tao-Chih Chang ; Chin-Yao Chang
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Wafer level chip stacked module by embedded IC packaging technology was studied in this paper. Wafers were treated to less than 50 mum thickness and then singulated. The prepared thin chips were stacked on to the base wafer and then embedded by dielectric layers (Ajinomoto build up film, ABF) lamination. Vias to both the pads on the analog chips and digital wafers were done by UV laser drilling process. After surface treatment and seed layer deposition, Cu plating process was adapted for the the via filling and traces patterning to form the interconnection between the chips and the component IO pads. Results of this study showed the benefits of the structure can provide more precise alignment and more reliable chip to wafer stacking without any voids or defects. Meanwhile, the presented wafer level process gives a much simple and cost effective package. By the described process integration, vertical chip stacked and embedded module within 300 mum thickness, excluding the solder ball, could be demonstrated. All the realization of this small size module will be revealed in detail. Severe reliability tests such as the 288degC solder dipping and 260degC level 3 pre-conditioning test were carried out to further clarify the component property. The corresponding failure analysis will be carried out to further clarify the key points of the whole demonstration.

Published in:

2007 International Microsystems, Packaging, Assembly and Circuits Technology

Date of Conference:

1-3 Oct. 2007