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This paper presents efficient reconfigurable architecture to perform discret wavelet transform. This architecture, which is based on FPGA technology, consists of a reconfigurable processing module, reconfigurable controller, data organization unit and adresse generator, and on chip memory. The reconfigurable address generator and controller handles a flexible and efficient address generation for an efficient data memory access and bandwidth. This architecture is scalable and allows processing of a continuous data flow in real time and for any number of levels. The practical working of the architecture is explained and its hardware implementation on Xilinx Virtex-5 FPGA is reported.
Date of Conference: 15-16 Nov. 2007