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An Efficient Implementation of Scalable Architecture for Discrete Wavelet Transform On FPGA

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4 Author(s)
Michael Guarisco ; Nancy University, Laboratoire d¿Instrumentation Electronique de Nancy (LIEN), Vandoeuvre-les-nancy, Nancy, 54500, email: michael.guarisco@lien.uhp-nancy.fr ; Xun Zhang ; Hassan Rabah ; Serge Weber

This paper presents efficient reconfigurable architecture to perform discret wavelet transform. This architecture, which is based on FPGA technology, consists of a reconfigurable processing module, reconfigurable controller, data organization unit and adresse generator, and on chip memory. The reconfigurable address generator and controller handles a flexible and efficient address generation for an efficient data memory access and bandwidth. This architecture is scalable and allows processing of a continuous data flow in real time and for any number of levels. The practical working of the architecture is explained and its hardware implementation on Xilinx Virtex-5 FPGA is reported.

Published in:

System-on-Chip, 2007. DCAS 2007. 6th IEEE Dallas Circuits and Systems Workshop on

Date of Conference:

15-16 Nov. 2007