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This paper is devoted to the analysis, implementation, and modeling of fully digital random bit generators based on recent research results on the design of stateless oscillator-based generators. A new approach to the data quality test is adopted where, instead of passing bunches of statistical tests on the raw data, the focus is on the verification of a minimum entropy limit for the delivered random numbers after the digital post-processing. The architecture of the proposed generator (noise source and post-processing algorithm) is described in detail and experimental results in a 90-nm CMOS process are reported. The fabricated device reaches a throughput of 1.74 Mb/s after post-processing with an area of 13000 mum2 and a power consumption of about 240 muW when running at its maximum speed. A statistical model for the noise source is provided and the entropy of the post-processed data has been evaluated obtaining an entropy per byte higher than 7.999.