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The Effect of Gate-Bias Stress and Temperature on the Performance of ZnO Thin-Film Transistors

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2 Author(s)
Richard B. M. Cross ; Emerging Technol. Res. Center, De Montfort Univ., Leicester ; Maria Merlyne De Souza

The stability of ZnO thin-film transistors is investigated by using gate-bias stress. It is found that the application of positive and negative stress results in the device transfer characteristics shifting in positive and negative directions, respectively. It is postulated that this device instability is a consequence of charge trapping at or near the channel/insulator interface. In addition, there is a degradation of subthreshold behavior and channel mobility, which is suggested to result from the defect-state creation within the ZnO layer. The effect of elevated temperature stress shows a predominance of interface-state creation in comparison to trapping under gate-bias stress. Device instability appears to be a consequence of the charging and discharging of preexisting trap states at the interface and in the channel region of the devices. All stressed devices recover their original characteristics after a short period at room temperature without the need for any thermal or bias annealing.

Published in:

IEEE Transactions on Device and Materials Reliability  (Volume:8 ,  Issue: 2 )