By Topic

A new fabrication method for multi-layer stacked devices using wafer-to-wafer stacked technology based on 8-inch wafers

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Maebashi, T. ; Honda Res. Inst. Japan Co. Ltd., Saitama ; Nakamura, N. ; Nakayama, S. ; Miyakawa, N.

This paper presents 3-layer stacked devices in which each wafer is stacked one after another, using 8.18 mum CMOS technology based on 8-inch wafers. Electrical conductivity between each layer was almost 100% and interconnection resistance was less than 0.7Omega between the upper and lower wafers with a Buried Interconnection (BI) and a micro-bump. The prototype devices showed sophisticated functionality by testing, and the ratio of functional devices in the stacked wafer reached more than 60 percent.

Published in:

Solid State Device Research Conference, 2007. ESSDERC 2007. 37th European

Date of Conference:

11-13 Sept. 2007