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A pipelined ADC architecture for use in sub-sampled systems which has its power scaleable with down sampled bandwidth is presented. Using a technique developed to eliminate the front end sample and hold, a power savings of >20% is achieved compared to a previous design. A technique to improve the settling behavior of Rapid Power on Opamps is also presented. Measured results in 1.8V 0.18 mum CMOS verify the removal of the front end sample and hold does not cause gross MSB errors for input frequencies higher than 267 MHz. With fs=50 MS/s, for fin=79 MHz the SNDR is 51.5 dB, and with fs=4.55 MS/s for fin=267 MHz the SNDR is 52.2 dB.