Cart (Loading....) | Create Account
Close category search window

A high bandwidth power scaleable sub-sampling 10-bit pipelined ADC with embedded sample and hold

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Ahmed, I. ; Univ. of Toronto, Toronto ; Johns, D.A.

A pipelined ADC architecture for use in sub-sampled systems which has its power scaleable with down sampled bandwidth is presented. Using a technique developed to eliminate the front end sample and hold, a power savings of >20% is achieved compared to a previous design. A technique to improve the settling behavior of Rapid Power on Opamps is also presented. Measured results in 1.8V 0.18 mum CMOS verify the removal of the front end sample and hold does not cause gross MSB errors for input frequencies higher than 267 MHz. With fs=50 MS/s, for fin=79 MHz the SNDR is 51.5 dB, and with fs=4.55 MS/s for fin=267 MHz the SNDR is 52.2 dB.

Published in:

Solid State Circuits Conference, 2007. ESSCIRC 2007. 33rd European

Date of Conference:

11-13 Sept. 2007

Need Help?

IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.