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A 1.2V 200-MS/s 10-bit folding and interpolating ADC in 0.13-μm CMOS

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3 Author(s)
Yihui Chen ; ETH Zurich, Zurich ; Qiuting Huang ; Burger, T.

This paper presents a folding and interpolating ADC in a 0.13-mum CMOS technology, which achieves 10-bit resolution and 200-MS/s sample rate despite the limitations of a 1.2 V supply voltage. The converter employs an open-loop auto- zero technique to cancel preamplifier offsets, and preamplifiers provide sufficient gain to overcome offsets from the following stages, which enable 8.6ENOB (53.5 dB SNDR) to be reached. The IC measures 3.24 mm2 including pads and consumes 195 mW in total.

Published in:

Solid State Circuits Conference, 2007. ESSCIRC 2007. 33rd European

Date of Conference:

11-13 Sept. 2007