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Intrinsic parameter fluctuations are already a limiting factor for 6-transistor SRAM scaling. In order to maintain the benefits of CMOS scaling, new SRAM cell designs are necessary. An 8-transistor SRAM cell structure is investigated and the impact of random doping fluctuations on its read and write noise margins, considering various supply voltages, are discussed. The results demonstrate impressive scalability, and indicate that the scaling window is still open for SRAM in the deca-nanometer regime.