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Summary form only given. Since the inventions of silicon memory devices at early 70s, silicon memory devices have been advanced with unprecedented pace which results in exponential growth of storage capacity of memory devices, and now they reach to 1 Gb density with 60 nm node for DRAM and 16 Gb density with 50 nm node for NAND Flash. During the evolution of silicon memory devices for the last 3 decades, silicon memory devices on-and-off faced critical challenges which seemed to be very difficult to surmount at initial stage, but those challenges were eventually cleared by appropriate cost-effective solutions and some of challenges paradigm shifted silicon memory technologies from simple and common planar technology to complicated and diversified technologies such as planar transistor with 3D capacitor and recently 3D transistor with 3D capacitor and etc. However, as the silicon technologies further enter deep nano-scale dimensions, silicon memory devices will encounter much critical challenges originated from ultimate limit of the transistor scaling and shallow margins in manufacturing due to ever-increasing fabrication costs resulting from technical complexities. Although there seems to be no unanimous solutions for silicon memory devices in future, most of experts working in silicon memory area, however, believe that silicon memory technology will be given right solutions down to a 20 nm node where a transistor contains only a small number of electrons, which is believed to be a practical limit to avoid noise errors owing to random telegraph noises, signal variations due to 1/radicn statistics, and fluctuations due to both rough edges of propagating lines and thickness variations and so forth. In addition, there are still many unknowns about the deep nano scaled memory devices. Thus, in this paper, in order to find the right directions of future semiconductor memory devices, key challenges and their possible solutions will be mainly discussed in views of basics a- nd key features of semiconductor memory devices, key technologies and designs.