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Model to Hardware matching for nano-meter scale technologies

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1 Author(s)
Sani R. Nassif ; IBM Research - Austin, 11501 Burnet Road, MS 904-6G021, Texas 78717, USA

With technology scaling becoming ever more difficult, the drive to continue to deliver performance and density has led to increasing technology complexity. Examples include the pervasive application of resolution enhancement techniques (RET) to enable sub-wavelength lithography and achieve circuit density, and strain engineering to improve device mobility and achieve circuit performance. The result of this increasing technology complexity has been a corresponding increase in the complexity of design/technology interaction. This phenomena demonstrates itself as a drastic increase in the number and complexity of design rules. Many of these rules are the result of the increase of the number and magnitude of systematic effects. In addition to these systematic sources of variability, we have an increasing host of random variations such as line edge roughness, which impacts channel lengths, and random dopant fluctuations, which impact threshold voltage. The net result has been a reduction in our ability to reliably predict the outcome of the manufacturing process. Given that the integrated circuit design process is based completely on our ability to create computer models of the expected behavior of a design, this gap in predictability is a source of grave concern. Model to hardware matching attempts to close this gap by developing techniques, tools, and design components which can be used to improve technology predictability.

Published in:

Solid State Circuits Conference, 2007. ESSCIRC 2007. 33rd European

Date of Conference:

11-13 Sept. 2007