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An Efficient SIMD Architecture with Parallel Memory for 2D Cosine Transforms of Video Coding

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5 Author(s)

This paper proposes an efficient SIMD architecture with parallel memory for 2D cosine transforms of multiple video standards. A novel parallel memory scheme is employed to provide conflict-free parallel access in both horizontal and vertical directions with the successive or even/odd mode, as well as to eliminate data permutation and matrix transposition. Furthermore, application specific instructions are presented to accelerate the transform kernels, such as butterfly and rotate operations with scaling, rounding and clipping. The simulation results show that proposed architecture achieves significant performance improvement with low hardware cost of 3.2 K equivalent gate count for parallel memory subsystem (not including SRAMs) and 19.8 K for arithmetic units@250 MHz in 0.18 mum process.

Published in:

Application -specific Systems, Architectures and Processors, 2007. ASAP. IEEE International Conf. on

Date of Conference:

9-11 July 2007