By Topic

Reconfigurable Motion Estimation Architecture for Multi-standard Video Compression

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Liang Lu ; Queen''s Univ., Belfast ; McCanny, J.V. ; Sezer, S.

A new, reconfigurable multi-standard architecture is introduced for integer-pixel motion estimation. This has been designed to cover most of the common block-based video compression standards, including MPEG-2, MPEG-4, H.264, WMV-9 andAVS. This is based on and extends a specific variable block-size architecture that we present for H.264 applications. The architecture exhibits simpler control, high throughput and relative low hardware cost when compared with existing circuits. It can also easily handle flexible search ranges without any increase in silicon area and can be configured prior to the start of the motion estimation process for a specific standard. The computational rates achieved make the circuit suitable for high end video processing applications such as HDTV. Silicon design studies indicate that circuits based on this approach incur only a relatively small penalty in terms of power dissipation and silicon area when compared with implementations for specific standards.

Published in:

Application -specific Systems, Architectures and Processors, 2007. ASAP. IEEE International Conf. on

Date of Conference:

9-11 July 2007