Skip to Main Content
This paper presents the design of a broadband power line communication (BPLC) receiver optimized for reduced hardware complexity. To this end, the Radio-Frequency (RF) stage uses a direct conversion architecture while some innovative solutions are used in the base-band signal processing, such as a new frequency offset synchronization scheme based on the frequency domain. Every part of the receiver has been optimized using a new non-commercial hardware-software co-simulation package named BROCOLI (Broadband Co-simulation Library) based on a set of hierarchical models, specially developed for this application. A prototype of the BPLC transceiver has been built and some experimental results are shown which validate the design process and the implemented solutions.