Cart (Loading....) | Create Account
Close category search window

Test cost efficiency exploration for CMT processors

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Jia Li ; CAS, Beijing ; Yu Hu ; Xiaowei Li

Chip multi-threading (CMT) is an architecture that can achieve overall high performance by exploiting high bandwidth rather than high frequency, thus reduce hardware complexity and power. Test cost of this architecture also can be reduced by efficiently utilizing its communication channel bandwidth during test. Because CMT architectures are designed low-power in nature, its testing should also be conducted under stringent power constraints. This paper discusses these above problems and proposes a cost-efficient test scheme. Experimental results show that our test scheme can achieve very short test time and low test data volume under stringent power constraints with low area overhead.

Published in:

TENCON 2007 - 2007 IEEE Region 10 Conference

Date of Conference:

Oct. 30 2007-Nov. 2 2007

Need Help?

IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.