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Efficient check node update implementation for normalized min-sum algorithm

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3 Author(s)
Lu Xin ; Shenzhen Institute of Information Technology, Shenzhen, China ; Liang Yongsheng ; Xu Jun

This paper has presented various min-sum related LDPC decoding algorithms and their typical hardware architectures of check node update in the scenario of parallel implementation. The m-to-2m decoder has been introduced to generate more efficient new hardware implementations of check node update, which can obviously reduce the number of multiplication operations for normalized min-sum algorithm for high rate LDPC codes. Simulations have claimed the performance of normalized min-sum is nearly the same as that of Log-BP, namely the optimal algorithm. In general, this paper has proved that normalized min-sum is good choices as LDPC decoding methods.

Published in:

TENCON 2007 - 2007 IEEE Region 10 Conference

Date of Conference:

Oct. 30 2007-Nov. 2 2007