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On-Chip Transient Detection Circuit for System-Level ESD Protection in CMOS Integrated Circuits to Meet Electromagnetic Compatibility Regulation

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3 Author(s)
Ming-Dou Ker ; Nat. Chiao-Tung Univ., Hsinchu ; Cheng-Cheng Yen ; Pi-Chia Shih

A new on-chip transient detection circuit for system-level electrostatic discharge (ESD) protection is proposed. The circuit performance to detect different positive and negative fast electrical transients has been investigated by the HSPICE simulator and verified in a silicon chip. The experimental results in a 0.13-m CMOS integrated circuit (IC) have confirmed that the proposed on-chip transient detection circuit can be used to detect fast electrical transients during the system-level ESD events. The proposed transient detection circuit can be further combined with the power-on reset circuit to improve the immunity of the CMOS IC products against system-level ESD stress.

Published in:

Electromagnetic Compatibility, IEEE Transactions on  (Volume:50 ,  Issue: 1 )