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The sectioned bus is an energy-optimal architecture for system-on-chip (SoC) communication, where we save energy by consequently switching off unused bus sections on a cycle-by-cycle basis. The communication processor is a paradigm for the control of such a bus by means of software. Synchronous communication takes place within the tiles of a SoC in the deep sub-micron technology domain. We explore design alternatives for a linear software-controlled sectioned bus while building the hardware model of a single-instruction-issue processor, and run, in simulation, a media benchmark on it. We determine the energy cost of controlling this bus, compare it with the energy gain obtained from the sectioning, and find it favorable. The control cost is only 5% of the bus transport energy, leaving us with a gain by segmentation of 81%. We demonstrate the feasibility of the control of a low-power synchronous communication system by the processor. Starting out from this case study at the low-end to medium range of network complexity, we consider the implications of growing complexity that will arise from using multiple sectioned buses on multiple-issue computers (VLIWs). We find that control of linear bus topologies of medium-level complexity is now well understood. Further work is needed at the high-end of non-linear topologies.