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Constraints imposed on various resources in embedded computing make it a challenging design space. One such important constraint is memory. Proper cache design can overcome this memory bottleneck. In our paper, we propose a methodology for cache design space exploration specific to cryptographic hash functions. The proposed methodology finds a speed-power optimized cache configuration. We also describe the experimental procedure towards formulation of the proposed exploration algorithm. Experiments are performed on two cryptographic hash functions, namely, SHA -1 and MD5. Our approach tries to reduce the exploration search space and hence is better than traditional exhaustive search.