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The authors in (B. Arslan and A. Orailuglu, 2004) propose circular-scan chain architecture to reduce test time and cost in SOCs. The technique presented in this paper is based on circular-scan architecture (B. Arslan and A. Orailuglu, 2004). The basic idea of circular-scan architecture is use of the captured response of the previously applied pattern as a template for the next pattern while allowing the full observation of the captured response. Proposed architecture achieves further compression by updating conflicting bits internally instead of using data Input pin. Experimental results showed an improvement between 3.5% to 7.8% in test data compression in 5 largest ISCAS89 circuits.