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In this paper we describe the design of an integrated 5.8 GIU low noise amplifier in 90 nm CMOS technology. The design is a tuned cascode LNA with on-chip matching that has a sufficiently low noise figure and high gain to enable high receiver sensitivity. The measured performance is NF=l.SdB, gain=28 dB, IIP3= -5 dBm and Pd=15mV; and NfW.SdB, gain=23 dB, HP3=-17 dBm and Pd=8 mV.
Published in:
Solid-State Circuits Conference, 2007. ASSCC '07. IEEE Asian
Date of Conference: 12-14 Nov. 2007
- Page(s):
- 99 - 102
- E-ISBN :
- 978-1-4244-1360-7
- Print ISBN:
- 978-1-4244-1360-7
- INSPEC Accession Number:
- 9812623
- Conference Location :
- Jeju
- Digital Object Identifier :
- 10.1109/ASSCC.2007.4425741
- Product Type:
- Conference Publications
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