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A 1.5dB NF, 5.8GHz CMOS low-noise amplifier with on-chip matching

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3 Author(s)
Duster, J.S. ; Intel Corp., Hillsboro ; Taylor, S.S. ; Zhan, H.C.

In this paper we describe the design of an integrated 5.8 GIU low noise amplifier in 90 nm CMOS technology. The design is a tuned cascode LNA with on-chip matching that has a sufficiently low noise figure and high gain to enable high receiver sensitivity. The measured performance is NF=l.SdB, gain=28 dB, IIP3= -5 dBm and Pd=15mV; and NfW.SdB, gain=23 dB, HP3=-17 dBm and Pd=8 mV.

Published in:

Solid-State Circuits Conference, 2007. ASSCC '07. IEEE Asian

Date of Conference:

12-14 Nov. 2007