By Topic

10 GSamples/s, 4-bit, 1.2V, design-for-testability ADC and DAC in 0.13µm CMOS technology

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Sheng-Chuan Liang ; Nat. Chiao Tung Univ. Hsinchu, Hsinchu ; Ding-Jyun Huang ; Chen-Kang Ho ; Hao-Chiao Hong

This paper demonstrates a 10 GS/s, 4-bit, flash analog-to-digital converter (ADC) and current-steering digital-to-analog converter (DAC) pair for the design of advanced serial-link transceivers. Current mode logic (CML) gates are used to alleviate the severe power bouncing. The active feedback amplifiers, CML, and wave-pipelining technique help achieve the ultimate 10 GHz sampling rate. A design-for-testability circuit using the digital loop-back scheme is added to address the difficulty of at-speed measurements. The experimental results show that the cascaded ADC and DAC pair achieves a 27.3 dBc spurious-free dynamic range and a 25.0 dB signal-to-noise ratio with the 1.11 GHz, -1 dBm stimulus. It corresponds to an ENOB of 3.86 bits. The test chip totally consumes 420 mW from a 1.2 V supply. The areas of the ADC and DAC are 0.1575 mm2 and 0.0636 mm2, respectively in 0.13 mum CMOS technology.

Published in:

Solid-State Circuits Conference, 2007. ASSCC '07. IEEE Asian

Date of Conference:

12-14 Nov. 2007