10 GSamples/s, 4-bit, 1.2V, design-for-testability ADC and DAC in 0.13µm CMOS technology

This paper demonstrates a 10GS/s, 4-bit, flash analog-to-digital converter (ADC) and current-steering digital-to-analog converter (DAC) pair for the design of advanced seriallink transceivers. Current mode logic (CML) gates are used to alleviate the severe power bouncing. The active feedback amplifiers, CML, and wave-pipelining technique help achieve the ultimate 10 GHz sampling rate. A design-for-testability circuit using the digital loop-back scheme is added to address the difficulty of at-speed measurements. The experimental results show that the cascaded ADC and DAC pair achieves a 27.3 dBc spurious-free dynamic range and a 25.0 dB signal-to-noise ratio with the 1.11 GHz, −1 dBm stimulus. It corresponds to an ENOB of 3.86 bits. The test chip totally consumes 420 mW from a 1.2V supply. The areas of the ADC and DAC are 0.1575 mm
²
and 0.0636 mm
²
, respectively in 0.13 µm CMOS technology.