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A passive filter for 10-Gb/s analog equalizer in 0.18-μm CMOS technology

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3 Author(s)
Jian-Hao Lu ; Graduate Institute of Electronics Engineering & Department of Electrical Engineering, National Taiwan University, Taipei, 10617 China ; Chi-Lun Luo ; Shen-Iuan Liu

In this paper, a high-speed and low-power analog equalizer for a 40-inch trace on FR4 board has been realized in 0.18-mum CMOS technology. In order to achieve the low-power purpose and compensate the large signal attenuation of the FR4 trace simultaneously, the equalizer is presented by using the proposed RLC passive filter. This passive filter is used to obtain an additional peaking at high frequencies without consuming any power. In addition, the active filter using capacitive degeneration and active feedback techniques is also utilized to compensate the broadband loss. This circuit achieves a data rate of 10-Gb/s and consumes 34.2 mW from a 1.8 V supply with the output swing up to 200 mVpldrp. The chip occupies 0.86times1.28 mm2 and the measured bit error rate (BER) is less than 10-12.

Published in:

Solid-State Circuits Conference, 2007. ASSCC '07. IEEE Asian

Date of Conference:

12-14 Nov. 2007