A passive filter for 10-Gb/s analog equalizer in 0.18-μm CMOS technology

In this paper, a high-speed and low-power analog equalizer for a 40-inch trace on FR4 board has been realized in 0.18-mum CMOS technology. In order to achieve the low-power purpose and compensate the large signal attenuation of the FR4 trace simultaneously, the equalizer is presented by using the proposed RLC passive filter. This passive filter is used to obtain an additional peaking at high frequencies without consuming any power. In addition, the active filter using capacitive degeneration and active feedback techniques is also utilized to compensate the broadband loss. This circuit achieves a data rate of 10-Gb/s and consumes 34.2 mW from a 1.8 V supply with the output swing up to 200 mV_pldrp. The chip occupies 0.86times1.28 mm² and the measured bit error rate (BER) is less than 10^-12.