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A 3.125 Gbps CMOS fully integrated optical receiver with adaptive analog equalizer

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8 Author(s)
Wei-Zen Chen ; Nat. Chiao Tung Univ., Hsin-Chu ; Shih-Hao Huang ; Guo-Wei Wu ; Chuan-Chang Liu
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This paper presents the design of a 3.125 Gbps monolithic CMOS optical receiver, integrating a photo detector, a transimpedance amplifier, and a post limiting amplifier on a single chip. The optical receiver is capable of delivering 420 inVpp to 50 Omega output load after optical to electrical conversion. High speed operation is achieved by utilizing spatial modulated light (SiVIL) detector and adaptive analog equalizer. Implemented in a 0.18 mum CMOS technology, the total power dissipation is 175 mW. The chip size is 0.7 mm2.

Published in:
Solid-State Circuits Conference, 2007. ASSCC '07. IEEE Asian

Date of Conference: 12-14 Nov. 2007

Page(s):
396 - 399
E-ISBN :
978-1-4244-1360-7
Print ISBN:
978-1-4244-1360-7
INSPEC Accession Number:
9812697
Conference Location :
Jeju
Digital Object Identifier :
10.1109/ASSCC.2007.4425714
Product Type:
Conference Publications

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