By Topic

A reconfigurable microcomputer system with PA3 (Programmable Autonomous Address-control-memory Architecture)

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Kawamura, Y. ; Renesas Technol. Corp., Tokyo

A programmable autonomous address-control-memory architecture (PA3) which supports memory based reconfigurable microcomputer (user structured microcomputer) is proposed. The PA3 provides finite autonomous device and executes the state transition control without CPU. The PA3 can be directly accessed as memory and support logic operation circuit of counter, and PWM, etc. When the logical function is mounted on silicon using the PA3, there is no need to relocate and rewire like FPGA. Each logic function module is achieved by loading the library which include logic function and wiring information. The performance depends on the characteristic of SRAM. The Standards bus interface of PA3 also supports both memory and peripheral buses in a microcomputer. The PA3 modeling and evaluation of the basic logical operation / function modules have been simulated.

Published in:

Solid-State Circuits Conference, 2007. ASSCC '07. IEEE Asian

Date of Conference:

12-14 Nov. 2007