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The key problem in the reverse analysis of encrypted programmable logic devices (PLDs) using logic analysis techniques is how to acquire effective and self-contained data set, especially for sequential PLDs. An efficient data acquisition algorithm is presented which suits for large scale and multi-state synchronous PLDs. The algorithm builds non-complete state graph and finds the shortest path for state migration from initial state to each active state. The algorithm has ideal time and space cost and has been used in our PLD reverse analysis system.