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A simple hardware-based statistical model on 65nm SOI CMOS technology

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12 Author(s)
Q. Liang ; IBM Semiconductor Res. & Dev. (SRDC), Hopewell Junction, NY 12533 & Essex Junction, VT, 05452, USA ; J. Johnson ; J. Walko ; M. Cai
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As CMOS devices further scale down, the variation of electrical parametric becomes significant and is critical for VLSI design. However, the difficulty in device statistical modeling also increases. The parasitics and second-order effect are not negligible, and the impact of process variations on device parametrics are usually correlated, which complicates the extraction of industry standard models (e.g. BSIM). Moreover, there is a critical trade-off on the number of independent variates in the model: too many variates makes the simulation and design impractical, while too few makes the statistics modeled incorrect. In this paper, for the first time, a novel strategy to determine the independent variates of the state-of-the-art CMOS technology without losing simplicity and accuracy is demonstrated, and a statistical modeling approach using these variates is presented. This modeling methodology is applied to characterize IBM 65nm SOI device. It directly shows major variations of the technology, and greatly reduces the model complexity. Moreover, it exhibits excellent model-hardware agreement on a large number of samples. The simplified model offers an explicit electrical approach to analyze the control of key process steps. It is well fit for advanced device technology characterization and VLSI design.

Published in:

Semiconductor Device Research Symposium, 2007 International

Date of Conference:

12-14 Dec. 2007