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In a standard process with a conventional rapid thermal annealing (RTA) stress engineering is a standard feature for advanced CMOS technologies to improve device performance (M. Horstmann et al., 2005). Unfortunately, such an annealing scheme does not meet the 32 nm node requirements due to thermal diffusion and solid solubility limitations. To solve the problem, technologies like flash lamp annealing (FLA)(T. Ito et al., 2003 ), laser annealing (A. Shima, 2006), and solid phase epitaxial regrowth (SPER) (A. Pouydebasque et al., 2005) have been intensively investigated as an alternative to RTA. Stress techniques like embedded SiGe (e-SiGe) and dual stress liner (DSL) are already implemented on diffusionless SOI-CMOS devices successfully. In (A. Wei et al., 2007), a new stress memorization technique (SMT) is used to induce tensile stress into the channel using a low temperature SPER process. The temperature for this stress memorization phenomenon is usually below 700degC and therefore, a negligible amount of dopant diffusion occurs. Thus, this stress technique could be also a method to enhance performance of a diffusionless n-MOSFET device further. This report shows for the first time the impact of an additional low temperature SPER annealing on device performance of non-diffusive flash-annealed MOSFETs.