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In this work, a 100 nm Ni layer was deposited on both Si-face and C-face of n-type doped low resistive (<30 mOmega-cm) 4H-SiC wafers by means of E-beam evaporation in a vacuum of the order of 10-7 Pa. These layer were patterned to form circular contacts and were cut in pieces to perform RTP annealing at different temperatures (800-1000 degC) in Ar ambient followed by I-V measurements to compare the contact resistances using the Kuphal method. To obtain identical conditions for Si-face and C-face during RTP annealing, the patterned substrate is sandwiched between two 4-inch Si carrier wafers. This novel setup can improve the temperature homogeneity on both sides of the SiC substrate during RTP annealing.