By Topic

Temperature dependant characteristics of scaled NMOS transistors with ultra-thin high-K dielectrics and metal gate electrodes

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)

This paper discusses the temperature dependence of the threshold voltage, electron mobility and gate leakage current for the scaled NMOS transistor, which has an interfacial SiO2 layer of 0.5 nm and an ALD (atomic layer deposition) fabricated HfO2 dielectric layer of 2.0 nm with a 10 nm TiN metal gate electrode covered by polysilicon.

Published in:

Semiconductor Device Research Symposium, 2007 International

Date of Conference:

12-14 Dec. 2007