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Run-Time Data-Dependent Defect Tolerance for Hybrid CMOS/Nanodevice Digital Memories

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3 Author(s)
Fei Sun ; Rensselaer Polytech. Inst., Troy ; Lu Feng ; Tong Zhang

This paper presents a data-dependent defect tolerance design approach to improve the storage capacity of defect-prone hybrid CMOS/nanodevice digital memories. The basic idea is to reduce the memory redundancy overhead by exploiting the run-time matching between the data and memory defects. A conditional bit-flipping technique is used to enable the practical realization of this design approach in presence of the conflict between the dynamic nature of run-time data-defect matching and static nature of memory system design. Computer simulations show that the proposed method can achieve much higher storage capacity compared with conventional data-independent defect tolerance at small memory operation overhead.

Published in:

IEEE Transactions on Nanotechnology  (Volume:7 ,  Issue: 2 )