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Low Vth HfSiON/TaSiN gate first stacks have been demonstrated, using atomic-layer-deposition (ALD) La2O3 cap layers, for half-pitch (hp) 32 nm-node metal gated bulk devices. By employing a very slow ALD-La2O3 growth rate (0.036 nm/cycle) within 30 cycles, the smallest equivalent oxide thickness (EOT< 0.7 nm) can be achieved with high electron carrier mobility and excellent Vth control (Vth< 0.31 V) that equals to SiO2/n-Poly Si devices. Thus, the drain currents are dramatically increased by using ALD-La2O3 cap layers. Moreover, the positive-bias-temperature-instability (PBTI ) over a 10-year lifetime can be held to an acceptably low level at Vg = + 1.0 V.
Date of Conference: 10-12 Dec. 2007