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A 32nm CMOS Low Power SoC Platform Technology for Foundry Applications with Functional High Density SRAM

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40 Author(s)
Shien-Yang Wu ; Taiwan Semicond. Manuf. Co., Hsin-Chu ; Chou, C.W. ; Lin, C.Y. ; Chiang, M.C.
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For the first time, we present a state-of-the-art 32 nm low power foundry technology integrated with 0.15um2 6-T high density SRAM, low standby transistors, analog/RF functions and Cu/low-k interconnect for mobile SoC applications. To our knowledge, this is the smallest fully functional 2Mb SRAM test-chip for 32nm node. Low power transistors with Lg of 30nm achieve current drive of 700/380 uA/um at 1.1V and off-leakage current of 1 nA/um for NMOS and PMOS, respectively. An NPoly/NWell MOS varactor shows capacitance ratio of >5.0. The MOM unit capacitance of 3.5 fF/um2 is achieved with only 4 metal layers.

Published in:

Electron Devices Meeting, 2007. IEDM 2007. IEEE International

Date of Conference:

10-12 Dec. 2007

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