Scheduled System Maintenance:
Some services will be unavailable Sunday, March 29th through Monday, March 30th. We apologize for the inconvenience.
By Topic

A highly scaled, high performance 45 nm bulk logic CMOS technology with 0.242 μm2 SRAM cell

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

38 Author(s)
Kuan-Lun Cheng ; Taiwan Semicond. Manuf. Co., Hsinchu ; Wu, C.C. ; Wang, Y.P. ; Lin, D.W.
more authors

A highly scaled, high performance 45 nm CMOS technology utilizing extensive immersion lithography to achieve the industry's highest scaling factor with ELK (k=2.55) BEOL is presented. A record gate density 2.4X higher than that of 65 nm is achieved. Refined strained-CMOS demonstrated 1200/750 μA/μm Idsat at 100 nA/μm Ioff, Vdd=1 V, which has the best Ion-Lg performance reported for bulk CMOS device. The proposed 45 nm technology is not only manufacturing friendly but also has well-controlled leakage and mismatch evidenced by a functional 32 Mb 0.242 μm2 SRAM.

Published in:

Electron Devices Meeting, 2007. IEDM 2007. IEEE International

Date of Conference:

10-12 Dec. 2007