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Junction Profile Engineering with a Novel Multiple Laser Spike Annealing Scheme for 45-nm Node High Performance and Low Leakage CMOS Technology

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14 Author(s)

We developed novel junction profile engineering that uses a newly developed multiple laser spike annealing scheme and applied it to 45-nm node high performance and low leakage CMOS technology. This novel junction profile engineering is effective for the performance improvement of CMOS devices with embedded SiGe in the PMOS regions. Reduction of the source-drain parasitic resistance and the junction leakage current were achieved, thus improving the Ion of 33-nm CMOS devices (8.2% / 12.8% with an Ioff = 9 [nA/mum] for PMOS / NMOS). We also demonstrate that the fluorine co-implant plays a large role in reducing the PMOS source-drain extension (SDE) resistance.

Published in:

Electron Devices Meeting, 2007. IEDM 2007. IEEE International

Date of Conference:

10-12 Dec. 2007

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