Scheduled System Maintenance on May 29th, 2015:
IEEE Xplore will be upgraded between 11:00 AM and 10:00 PM EDT. During this time there may be intermittent impact on performance. We apologize for any inconvenience.
By Topic

Performance Analysis of III-V Materials in a Double-Gate nano-MOSFET

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

6 Author(s)

Nanoscale double-gate n-MOSFETs with silicon and III-V (GaAs and InAs) channels are studied using numerical simulation. The device structures are based on the ITRS 14 nm node (year 2020), and are simulated using the program nanoMOS, which utilizes the NEGF technique for treating ballistic electron transport in the channel. The effective masses used are obtained by extraction from the full band structure using the sp3d5s* empirical tight-binding method. This process returns effective mass values for all valleys which are far more accurate than bulk values for the ultra- thin-body MOSFET. The results indicate that for digital logic applications, III-V materials offer little or no performance advantage over silicon for ballistic devices near the channel length scaling limit.

Published in:

Electron Devices Meeting, 2007. IEDM 2007. IEEE International

Date of Conference:

10-12 Dec. 2007