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Performance Analysis of III-V Materials in a Double-Gate nano-MOSFET

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6 Author(s)
Kurtis D. Cantley ; School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA; Department of Electrical Engineering, University of Texas at Dallas, Richardson, TX, USA. E-mail: ; Yang Liu ; Himadri S. Pal ; Tony Low
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Nanoscale double-gate n-MOSFETs with silicon and III-V (GaAs and InAs) channels are studied using numerical simulation. The device structures are based on the ITRS 14 nm node (year 2020), and are simulated using the program nanoMOS, which utilizes the NEGF technique for treating ballistic electron transport in the channel. The effective masses used are obtained by extraction from the full band structure using the sp3d5s* empirical tight-binding method. This process returns effective mass values for all valleys which are far more accurate than bulk values for the ultra- thin-body MOSFET. The results indicate that for digital logic applications, III-V materials offer little or no performance advantage over silicon for ballistic devices near the channel length scaling limit.

Published in:

2007 IEEE International Electron Devices Meeting

Date of Conference:

10-12 Dec. 2007