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A gate-first process was used to fabricate CMOS circuits with high performing high-K and metal gate transistors. Symmetric low VT values of plusmn 0.25 V and unstrained IDSAT of 1035/500 muA/mum for nMOS/pMOS at IOFF=100nA/mum and |VDD|=1.1 V are demonstrated on a single wafer. This was achieved using Hf-based high-k dielectrics with La (nMOS) and Al (pMOS) doping, in combination with a laser-only activation anneal to maintain band-edge EWF and minimal EOT re-growth. The laser-only anneal further results in improved LG scaling of 15 nm and a 2 Aring TINV reduction over the spike reference.