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A novel cell arrangement enabling Trench DRAM scaling to 40nm and beyond

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19 Author(s)
Heineck, L. ; Qimonda Dresden GmbH & Co. OHG, Munich ; Graf, W. ; Popp, M. ; Savignac, D.
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We present for the first time the full integration scheme and 512 Mb product data for a trench DRAM technology targeting the 48 nm node. The key technology enablers are a new cell architecture "wordline over bitline" (WOB) realizing a high degree of self-alignment and small parasitic capacitances, together with high performance periphery devices at reduced internal voltage, and the integration of a MIC/HfSiO trench capacitor.

Published in:

Electron Devices Meeting, 2007. IEDM 2007. IEEE International

Date of Conference:

10-12 Dec. 2007