By Topic

Real-time simulation of finite-element analysis permanent magnet synchronous machine drives on a FPGA card

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Christian Dufour ; Opal-RT Technologies, 1751 Richardson, suite 2525, Montréal (Quéec), Canada ; Jean Belanger ; Simon Abourida ; Vincent Lapointe

This paper presents a real-time simulator of a permanent magnet synchronous motor (PMSM) drive based on a finite- element analysis (FEA) method and implemented on an FPGA card for HIL testing of motor drive controllers. The proposed PMSM model is a phase domain model with inductances and flux profiles computed from the JMAG-RT finite element analysis software. A 3-phase IGBT inverter drives the PMSM machine. Both models are implemented on an FPGA chip, with no VHDL coding, using the RT-LAB real-time simulation platform from Opal-RT and a Simulink blockset called Xilinx System Generator (XSG). The PMSM drive, along with an open-loop test source for the pulse width modulation, is coded for an FPGA card. The PMSM drive is completed with various encoder models (quadrature, Hall effects and resolver). The overall model compilation and simulation is entirely automated by RT-LAB. The drive is designed to run in a closed loop with a HIL-interfaced controller connected to the I/O of the real-time simulator. The PMSM drive model runs with an equivalent 10 nanosecond time step (100 MHz FPGA card) and has a latency of 300 ns (PMSM machine and inverter) with the exception of the FEA-computed inductance matrix routines which are updated in parallel on a CPU of the real-time simulator at a 40 us rate. The motor drive is directly connected to digital inputs and analog outputs with 1 microsecond settling time on the FPGA card and has a resulting total hardware-in-the-loop latency of 1.3 microseconds.

Published in:

Power Electronics and Applications, 2007 European Conference on

Date of Conference:

2-5 Sept. 2007