Skip to Main Content
Summary form only given. Design for low power has become a key requirement in today's SoC design, especially for mobile applications. Multi-Vdd is an effective method to reduce both leakage and dynamic power, by assigning different supply voltages to cells according to their timing criticality. In a multi-Vdd design, cells of different supply voltage are often grouped into small number of voltage islands (each having a single supply voltage), in order to avoid complex power supply system and excessive amount of level shifters (as the former would cause increase in design cost and the latter would cause extra overhead in area, delay and power). In this talk, we present a low power design methodology which manages power, timing and design cost by using multi-Vdd and voltage islands. We first present an algorithm that in a multi-Vdd design with cells assigned different supply voltage according to their timing criticality, automatically group the cells into a set of voltage islands that balance the power versus design cost tradeoff under performance requirement. One prerequisite of the voltage island grouping algorithm, is an initial voltage assignment at the standard cell level that meets timing. In the second part of this talk, we present a method to produce an initial voltage assignment which not only meets timing but also forms good proximity of high voltage cells to provide the voltage island grouping algorithm with a smooth input. Although the voltage assignment algorithm tries to form good proximity of high voltage cells for better voltage island grouping, however, sometimes a few isolated critical cells (called outlier) may still exists in the resulting voltage assignment, causing disproportionately expensive penalty to the final voltage island grouping. In the last part of this talk, we propose an algorithm to improve the voltage assignment by automatic outlier detection followed by incremental placement. Experimental results on industrial circuits will be pre- sented.